ON Semiconductor Fabrication
Technology descriptions, MPW fabrication schedule, and vendor document access procedures for the ON Semiconductor fabrication processes available through MOSIS.
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Technology descriptions, MPW fabrication schedule, and vendor document access procedures for the ON Semiconductor fabrication processes available through MOSIS.
The ON Semiconductor fabrication processes available through MOSIS include 0.7 µm high voltage CMOS, 0.5 µm CMOS, and 0.35 µm high voltage CMOS.
MOSIS offers access to the ON Semiconductor multiproject wafer (MPW) runs. To be considered ontime for an MPW run, layout and paperwork are due to MOSIS by 1 PM PT (Pacific/California Time) on the date listed.
ON Semiconductor design kits are available upon approval for MOSIS customers.
General instructions for accessing ON Semiconductor design rules and cell libraries through MOSIS.
The ON Semiconductor C5 process offered through MOSIS supports designs subject to export control under ITAR regulations.