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MOSIS FAQs
Spice Model Parameters
Test Data and SPICE Parameters from Previous Runs
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1.0
Which SPICE parameters will give more accurate simulations?
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2.0
Does MOSIS release BSIM3 parameters compatible with Berkeley SPICE?
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3.0
Why do I get error messages when I put in PSpice simulators?
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4.0
How can I obtain SPICE noise parameters for MOSIS processes?
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5.0
How can I improve the accuracy of sub-threshold simulations?
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6.0
What value should I use for WD (lateral diffusion into channel width)?
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7.0
What options are set in the input decks for circuit simulations?
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8.0
Where can I find SPICE temperature parameters for MOSIS processes?
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9.0
Are MOSIS SPICE BSIM3 parameters accurate enough for analog and RF
designs?
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10.0
Does MOSIS provide SPICE model parameters for the NPN transistors
available in some MOSIS technologies or for any bipolar devices?
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11.0
What are the frequency limits for MOSIS SPICE parameters?
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12.0
How do I use XL and XW in my SPICE simulations? My simulator does not
recognize them.
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13.0
I am accustomed to calculating an effective channel length
(L_effective) according to the formula:
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L_effective = L_drawn + XL - (2 * LD)
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How can I derive this quantity from the MOSIS on-line SPICE BSIM3
parameters, which do not include LD?
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14.0
Does the Agilent ADS kit supports PSPICE?
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1.0 I have SPICE BSIM2 parameters for a MOSIS process, and I also have
the MOSIS BSIM3 parameters for the wafer lot that contained my
design. Which parameters will give the more accurate simulations?
The University
of California at Berkeley BSIM3 web site includes a comparison of
the merits of BSIM2 and BSIM3.
Which is more accurate? The answer to that question in any particular
case depends on the particulars of the case (how accurate is the
netlist, especially the parasitics, what are the critical circuit
nodes and how well are they characterized, etc.).
In general, BSIM3 CAN be more accurate, but in particular, if your
circuit behavior depends on devices with geometries outside the range
of focus of MOSIS parameter optimization strategies (currently
dimensions less than 20 micrometers, but this is subject to change),
then a binned set of BSIM2 parameters may be better.
A comparison of simulation results using MOSIS BSIM3 parameters
from several wafer lots can provide useful information about the
effects of process variations on the performance of your design.
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2.0 The header for the SPICE BSIM3v3 model cards posted on the
MOSIS web pages says "SPICE BSIM3 Version 3.1 (HSPICE Level 49)
Parameters," and the parameters include Level=49. My simulator does
not recognize Level=49. Does MOSIS release BSIM3 parameters compatible
with Berkeley SPICE?
MOSIS BSIM3v3 parameters are released as LEVEL=49 because our
simulations are run in Star-HSPICE and because many users have that
tool. The parameters themselves, however, are Berkeley-compatible and
are not HSPICE-specific.
If you have tried this without success, please send a message to
support@mosis.com which
includes the error messages generated by your SPICE simulator and your
SPICE input files if possible.
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3.0 Why do I get error messages when I put in PSpice simulators?
MOSIS supports industry standard LEVEL49 BSIM3v3.1 model
parameters. Most simulation tools also support LEVEL49, but
PSPICE requires some changes on the parameters. To get detail
information on how to convert LEVEL49 model to PSPICE, download the
document "Tips for Converting LEVEL49
Models to LEVEL7 PSpice Models"
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4.0 How can I obtain SPICE noise parameters for MOSIS processes?
MOSIS does not extract MOS noise model parameters at this time. Some
vendor models are available to MOSIS Customers with signed
non-disclosure agreements from the MOSIS Secure Document Server at
https://www.mosis.com/Webforms/document_access.html.
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5.0 How can I improve the accuracy of sub-threshold simulations
using MOSIS-provided SPICE parameters?
MOSIS lot-specific SPICE parameters will yield more accurate
simulations with digital circuits than with analog.
We do not currently optimize specifically the sub-threshold parameters
in the MOSIS BSIM3v3 model cards, and we do not verify sub-threshold
performance against measurements. These are certainly things we
intend to implement, but resource limits prevent us from doing so at
this time.
MOSIS customers can obtain vendor-provided SPICE parameters when they
are available. These are not lot-specific, but in some cases they are
extensively binned and contain corner sets, and they may provide more
accurate simulations for devices of given specific dimensions.
To obtain these parameters, please see
vendor-specific agreements,
applications, and procedures for requesting access to proprietary
vendor documents available through MOSIS.
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6.0 MOSIS Level 3 SPICE parameters do not include WD (lateral
diffusion into the channel width). What value should I use for this
parameter?
WD is not included in the MOSIS Level 3 model card in order to
maintain compatibility with Berkeley SPICE.
At the end of the NMOS and PMOS parameter lists, we include as
comments delta W values determined elecrtically during parametric
test. Use these numbers either to adjust the device widths in your
netlist or to derive WD and add it to your model card, where WD is one
half of delta W.
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7.0 What options are set in the input decks for circuit
simulations used for verifying MOSIS SPICE parameters?
.OPTION SPICE
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8.0 The temperature parameters in the MOSIS SPICE model cards are
set to the default values. Where can I find extracted SPICE
temperature parameters for MOSIS processes?
MOSIS extracts and optimizes SPICE BSIM3v3 parameters for each wafer
lot.
Our normal practice at this time does not include the extraction of
temperature parameters. We do have a procedure in place for this,
however, and we did release extracted temperature parameters for the
AMI CWL run
N87R and the HP AMOS14TB run
N84A.
You can find them in the model card for those lots in our technical
support web pages. Connect to http://www.mosis.com and select
Electrical Parameters from the
Information section in the grey menu column on the left side of the
page.
For N84A select the HP 0.5 (AMOS14) micron process and for N87R select
the AMI 0.8 micron (CWL) process.
MOSIS customers who have signed a non-disclosure agreement may obtain
the wafer fabricator's SPICE parameters, if they are available, by
requesting them from MOSIS. Foundry model cards usually contain
temperature parameters. For more information send e-mail to
support@mosis.com and include
your MOSIS Customer Account ID in the message.
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9.0 Are MOSIS SPICE BSIM3 parameters accurate enough for analog
and RF designs?
The focus of the MOSIS BSIM3 parameter extraction and optimization
strategies to date has been basic DC characterization and digital
simulations. For critical designs the wafer fabricator's SPICE
parameters may be more accurate, not only because they may be more
precisely tuned to particular process features like the channel doping
concentration (NCH), but also because they are binned and thus may fit
specific device geometries better.
We expect that MOSIS SPICE parameters will be applied more and more to
analog and RF circuits, and we are turning our efforts in that
direction as time and resources permit.
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10.0 Does MOSIS provide SPICE model parameters for the NPN
transistors available in some MOSIS technologies or for any bipolar
devices?
Model parameter extraction and optimization efforts at MOSIS are
limited at this time to MOS devices.
Some MOSIS wafer fabricators permit us to release foundry models, when
they are available, to registered MOSIS customers. For further
information, inquire at
support@mosis.com. Be sure to
mention your MOSIS account number and the process technology you are
planning to use.
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11.0 What are the frequency limits for MOSIS SPICE parameters?
MOSIS BSIM3 SPICE parameters are not verified for circuit behavior
above 500 MHz, and no specific optimization for high frequency device
performance is carried out at this time.
As resources permit, we plan to examine more carefully the accuracy of
our parameters at frequencies above 100 MHz, and in addition MOSIS
expects to provide S-parameters for sub-micrometer technologies over a
range from 100 MHz to 50 GHz.
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12.0 How do I use XL and XW in my SPICE simulations? My simulator
does not recognize them.
XL and XW are terms which incorporate known mask and process biases to
correct drawn transistor channel dimensions to fabricated dimensions.
(XL and XW are "quasi-SPICE" parameters, which originated with HSPICE,
but which many simulators have adopted by convention.)
If XL and XW are given in the model card, the simulator adds XL to all
channel lengths in the net list, and XW to all the channel widths.
For example, if a given process produces physical gates that are 0.1
micrometer shorter than the drawn length for a given set of design
rules, then XL will have a value of -0.1 micrometer.
When working with the MOSIS Scalable CMOS (SCMOS) rules, the XL and XW
values for each applicable MOSIS Design Technology are given in the
parametric summaries for each MOSIS run at
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http://www.mosis.com/Technical/Testdata/
Many simulators recognize XL and XW, and we include them in our SPICE
BSIM3 model cards because it is the simplest way for us to provide
this information to designers working with varying combinations of
design rules and design tools.
To use the MOSIS BSIM3 parameters with Berkeley SPICE3f5, or any
simulator that does not recognize XL and XW, you must add the
appropriate XL and XW values to the geometric specifications for each
device in your net list, and then remove XL and XW from the model
card. If a given device has a drawn channel width of 4.0 micrometers,
for example, and XW = 0.2, then you must modify the net list so that
the channel width for that device is 4.2 micrometers.
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13.0 I am accustomed to calculating an effective channel length
(L_effective) according to the formula:
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L_effective = L_drawn + XL - (2 * LD)
How can I derive this quantity from the MOSIS on-line SPICE BSIM3
parameters, which do not include LD?
There are many ways to define, calculate, estimate, and measure
effective MOS channel dimensions, some biased more toward physical
properties of the devices and some more toward goodness of fit of a
particular model.
The formula above is valid for SPICE Level 3 and similar models,
but is not applicable for BSIM3v3 because BSIM3v3 does not have an
LD parameter, where LD represents the portion of the source-drain
active area that lies under the gate,
The simple BSIM3v3 analog of LD is LINT, which we do extract and
optimize.
The formula for effective channel length with MOSIS BSIM3v3
parameters is
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L_effective = L_drawn - (2 * LINT)
(For this discussion we have simplified this expression somewhat.
BSIM3v3 permits several more terms. Note that XL, which is not a
BSIM3 parameter, but which is recognized by some modeling tools as
a mask and process geometric bias factor (see FAQ on XL, XW), does
not appear in the equation because it is incorporated into LINT
during parameter extraction and optimization.)
Keep in mind that a process descriptor like "0.18 micron" is an
approximation of the actual physical and-or effective electrical
dimensions, the precise meaning of which varies considerably from
vendor to vendor and from process to process and from NMOS to PMOS
devices.
Also keep in mind that values for LINT, WINT, and other model
parameters may be determined as much or more by the specific
extraction and optimization procedures used to produce them as they
are by the physical characteristics of the devices. A small change in
a parameter optimization strategy can produce relatively large changes
in LINT, for example, while still resulting in an overall set of model
parameters that fits reasonably well.
In other words, you cannot properly interpret LINT, or the L_effective
calculated from it, without considering the entire measurement process
and extraction and optimization procedures that produced it.
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14.0 Does the Agilent ADS kit supports PSPICE?
Yes. Please see
http://cp.literature.agilent.com/litweb/pdf/ads2002/netlist/net0823.html
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Related Links
FAQ: Wafer Electrical Specifications
BSIM3v3.1 Model Parameter Extraction & Optimization (pdf)
Test Data and SPICE Parameters from Previous Runs
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