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General Information About MOSIS Products Processes Prices Support User Group Events Job Openings News Work with MOSIS Getting Started Design and Test Requests Run Status NEW! Account Status Project Status Test Data Docs and Forms Documents Forms/Agreements Web Forms Quick Reference New Users Experienced Users Purchasing Agents Design and Test Academic Institutions Export Program Submit A Project Search MOSIS	Taiwan Semiconductor (TSMC) 0.35 Micron CL035HV Process 1. CL035HV Process Description This process is the TSMC 0.35 2P4M 3.3/15 V high voltage process, has 2 poly layers and 4 metals. This processes uses non-epitaxial wafers. 2. TSMC Design Rules, Process Specifications, and SPICE Parameters TSMC has sub-licensed MOSIS to distribute this information to approved customers who have an account with MOSIS and submit the online TSMC Access Request form. Review the following CMP and antenna guidelines which apply to this process. Design rules supported by this technology Only the TSMC design rules will be supported for this technology. MOSIS Technology Codes See Technology Codes for TSMC CL035HV Process. 3. Parametric Test Results and SPICE Model Parameters Contact support@mosis.com. 4. Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness TSMC CL035HV Process Wafer Size (inches) Reticle Size (millimeters, approx.) Reticle Copies Stepped on Wafer (approx.) Turn- around Time (weeks, approx.) Die Thickness (+/- .5 mil) Wafer Thickness Mils Micro- meters Mils Micro- meters 8 21 x 21 * 55 13 - 12 10 250 30 760   * Smaller sizes are available. Related Links MOSIS-Supported TSMC Processes TSMC Technology Codes & Layer Maps TSMC Document Access
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