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AMI Semiconductor
0.35 Micron
I3T80 Process
1. Process Description
This CMOS process has 4 metal layers. The process
offers MiM capacitor, high resistive poly, and 3.3 volt digital
core and I/O's. A thick oxide layer is used for DMOS gate
transistors. DMOS devices for 80 volt, NPN and PNP transistor are
available.
2. Design Rules
This process support the following design rules
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Design Rules
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Lambda
(micro- meter)
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Feature Size
(micro- meter)
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Available
From
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AMIS rules
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None
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0.35
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MOSIS (See Section 3)
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MOSIS Technology Codes
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See
Technology
Codes for AMIS I3T80 0.35 Micron Process.
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Important note about insulator layers
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On this process, AMIS requires that all features on the insulator
layers (CONTACT, VIA) be of the single standard size. There are no
exceptions for pads, logos, or anything else. Large openings are to be
replaced by an array of standard sized openings.
3.
AMIS Design Rules, Process Specifications, and SPICE
Parameters
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AMIS has sub-licensed MOSIS to distribute this information to
customers who do not have a
MyAMIS account. To obtain
any of these items you must have an account with MOSIS, submit the
on-line AMIS Access Request, then sign both the Confidentiality
Agreement (CDA) and Design Kit License Agreement (DKLA).
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4. Parametric Test Results and SPICE Model Parameters
To be provided when available.
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Related Links
MOSIS-Supported AMIS Processes
AMIS Technology
Codes & Layer Maps
AMIS Document Access
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