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AMI Semiconductor
0.35 Micron
C3O Process
This process is available for dedicated runs, but not multi-project
wafer runs.
1. Process Description
This non-silicided CMOS process has 4 metal layers and 2 poly layers
with a poly resistor. Stacked contacts are supported. The
process is for 3.3 volt applications. PiP (poly2 over poly) capacitors
(950 aF/µm²) are available. Wafers are epitaxial for this
process. For further information, see the
AMIS Mixed Signal Foundry Services web page.
2. Design Rules
This process support the following design rules
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Design Rules
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Lambda
(micro- meter)
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Feature Size
(micro- meter)
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Available
From
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SCMOS_SUBM
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0.20
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0.40
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MOSIS in
HTML
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SCMOS
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0.25
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0.50
(after sizing)
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MOSIS in
HTML
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AMI_C3 Rules
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n/a
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0.4
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AMIS (See Section 3)
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Review the
CMP and antenna guidelines which apply to both sets of design
rules.
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Please note changes to the SCMOS rules for selected layers. The value
of lambda is larger for these rules as mapped to C3O.
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Design Rule Name
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SCMOS_SUBM Rule
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SUBM (non C3O) Lambda Value
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SUBM (for C3O) Lambda Value
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N_WELL
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1.2
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18
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21
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1.3
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6
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11
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POLY2
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11.1
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7
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10
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11.2, 12.2
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3
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4
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11.3
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5
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6
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N_PLUS_SELECT, P_PLUS_SELECT
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4.4
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2
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3
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Design Rule Name
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SCMOS Rule
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SCMOS (non C3O) Lambda Value
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SCMOS (for C3O) Lambda Value
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N_WELL
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1.2
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9
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16
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1.3
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6
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8
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POLY2
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11.1
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3
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8
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11.2, 12.2
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3
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4
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11.3
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2
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5
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MOSIS Technology Codes
See
Technology Codes for AMIS C3O Process.
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Important note about insulator layer
On this process, AMIS requires that all features on the insulator
layers (CONTACT, VIA, VIA2, VIA3) be of the single standard
size. There are no exceptions for pads, logos, or anything else. Large
openings are to be replaced by an array of standard sized openings.
3. AMIS Design Rules, Process Specifications, and SPICE
Parameters
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AMIS has sub-licensed MOSIS to distribute this information to
customers who do not have a
MyAMIS account. To obtain
any of these items you must have an account with MOSIS, submit the
on-line AMIS Access Request, then sign both the Confidentiality
Agreement (CDA) and Design Kit License Agreement (DKLA).
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4. Parametric Test Results and SPICE Model Parameters
See Test Results for
AMIS C3O runs.
5. Reticle/Wafer Size, Steps, Turnaround Time, Wafer and Die Thickness
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AMIS C3O Process
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Wafer Size
(inches)
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Reticle Size (mili- meters, approx.)
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Reticle Copies Stepped on Wafer (approx.)
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Turn- around Time (weeks, approx.)
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Die Thickness
(+/- .5 mil)
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Wafer Thickness
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Mils
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Micro- meters
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Mils
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Micro- meters
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8
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21 x 21
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55
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10 - 12
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10
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250
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30
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760
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Related Links
MOSIS-Supported AMIS Processes
AMIS Technology
Codes & Layer Maps
AMIS Document Access
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