Processes That Also Support SCMOS Rules
Processes offered by MOSIS that also support SCMOS rules.
MOSIS Scalable CMOS (SCMOS) is a set of logical layers together with their design rules, which provide a nearly process- and metric-independent interface to many CMOS fabrication processes available through MOSIS.
Only some of the processes offered by MOSIS support the SCMOS vendor-independent, scalable rules layout rules.
Use SCMOS layers and rules for portability and simplicity. Use vendor specific rules for fine-tuned layout and for those processes that support only their native layers and rule set. Not all vendor layers are supported by SCMOS rules and layers.
If a technology is not listed, it is not supported by SCMOS rules.
| Foundry | Comparable Process1 | Technology Code | Layer Map |
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| TSMC | 0.35 micron, 1P4M, Silicided, CL035 (TSMC35_SIL) | SCN4M, SCN4M_SUBM | See SCN4M map |
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| 0.35 micron, 2P4M, Polycided CM035 (TSMC35_P2) | SCN4ME, SCN4ME_SUBM | See SCN4ME map | |
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| 0.25 micron, 1P5M, CL025/CR025 (CM025) | SCN5M_SUBM, SCN5M_DEEP | See SCN5M map | |
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| 0.18 micron 1P6M CL018 CR018 (CM018) | SCN6M_SUBM, SCN6M_DEEP | See SCN6M map | |
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| ON Semi | 0.50 micron, 1P3M, C5 | SCN3M, SCN3M_SUBM | See SCN3M map |
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| 0.50 micron, 2P3M, C5 | SCN3ME, SCN3ME_SUBM | See SCN3ME map | |
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1 MOSIS has not issued SCMOS design rules for some vendor-supported options. Most non-standard options (as, medium threshold voltage) are available only for projects designed using the vendor set of layers and rules. |
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