MOSIS Process Monitor
C O N T E N T S
1.0 Introduction
2.0 DC Parametric Test Structures
3.0 AC Parametric Test Structures
4.0 Functional Test Structures
5.0 Test Structure Identification
6.0 Test Index
Figure 1: Sample Contact (N+ Active to Metal) Kelvin Bridge
Figure 2: Sample Sheet Resistance Line Width Bridge (Metal1)
Figure 3: Sample Step Coverage (Metal 2 - Metal 3)
Figure 4: Sample (N Enhancement) Common Transistor(s)
Figure 5: Sample (N Enhancement) Isolated Transistor(s)
Figure 6: N_ACT/P_ACT Field Oxide Transistor Pair
Figure 7: Test Inverter(s)
Figure 8: Sample Calibration Capacitor (Floating)
Figure 9: Sample Area Capacitor (POLY to P_PLUS_ACTIVE)
Figure 10: Sample Fringe Capacitor (P_PLUS_ACTIVE to N_WELL)
Figure 11: Functional Test Area
Figure 12: Sample Ring Oscillator (Inverter)
1.0 Introduction
The MOSIS Process Monitor (PM) consists of an array of DC and AC parametric test structures and a small number of functional test devices for monitoring fabrication of wafers by MOSIS foundries. These tests are designed to monitor all of the parameters in the vendor specifications for each supported process.
1.1 PARAMETRIC MONITORS AND PROBING ORGANIZATION
The test structures and tests described here are a basic parametric monitor set. This set is representative of the generic classes of structures required to monitor CMOS wafer fabrication.
There are three classes of test devices: DC parametric, AC parametric, and functional. Each class of test device has its own group of probe card pins. The DC parametric area consists of a 2 x 10 pad group that is tested entirely by instrumentation within a parametric tester. The AC parametric area (capacitors) consists of a 2 x 3 pad group connected through isolation relays to a Hewlett Packard 4275A LCR meter which communicates with the test system through an IEEE-488 interface. The functional device test area consists of a 2 x 10 pad group that connects to an IMS functional test system and an HP frequency counter. Both of these instruments communicate with the parametric test system through an IEEE-488 interface. This functional device test area is configured with pre-assigned pins to simplify functional tester programming and interfacing. Pin assignments for the functional pad group are included in section 1.4, Functional Test Structures.
Probe pads are 80 µm square on a 160-µm pitch.
The set of test structures described in this document is a library for
designing PMs for particular requirements. MOSIS technologies that use
full wafer masks have a rich set of structures in a full die dropin
PM; with reticle (step and repeat) masks a minimal set of test
structures are placed in a small test strip. In either case, wafer
monitoring (or selection) requires at least the following
measurements:
INTERCONNECT PARAMETERS:
STEP COVERAGE:
TRANSISTOR CHARACTERISTICS:
FIELD OXIDE TRANSISTORS:
INVERTERS:
CAPACITORS:
RING OSCILLATOR:
2.0 DC Parametric Test Structures
2.1 CONTACT RESISTANCE BRIDGES
The contact resistance bridges are Kelvin-connected contact resistors with a single (nominal design rule) contact between two connected layers on the chip. Two variations of contact resistors are available: one with large overlap around the contact, and the other with minimum overlap allowed by the design rules. The contact resistor with the large overlap is used to measure the interfacial resistance of the contact itself. Contacts with minimum overlap have an additional resistance component caused by current crowding within the minimum overlap region.
For large overlap contacts, the upper layer is run in a 'dogleg' (bent 90 degrees in the center) bar of 15 µm width with a minimum contact (or via) placed in the center of the right angle jog. The connected layer is constructed with an identical structure rotated 180 degrees with the center overlapping the metal. The width of this layer is also 15 µm. The ends of the four bars are each connected to separate probe pads.
Minimum overlap contacts are constructed by replacing the center overlap region of the large overlap contact with a minimum overlap contact structure, connected to the 15 µm width bars with a short length of minimum design rule width wire.
See Figure 1: Sample Contact (N+ Active to Metal) Kelvin Bridge
2.1.1 TESTING
Testing is performed by passing constant current through the contact between the two layers and measuring the resulting voltage. The constant current source is attached to two opposite arms (different layers) of the bridge and the resulting voltage is measured between the remaining two arms. With the current source at zero, the thermal voltage in the test structure is measured and later subtracted from the measured voltage. Current is passed in two directions and the measured voltages are summed (preserving the sign) to determine if the contact is partially rectifying.
The resistance measured with the current in the positive direction and
the voltage sum are reported.
Voltage Sum: VSUM = V(+IFORCE) + V(IFORCE)
- IFORCE = 1.0 mA for cuts (M1/P+, M1/N+, M1/Poly), 10.0 mA for vias (M1/M2, M2/M3)
2.2 SHEET RESISTANCE - LINE WIDTH BRIDGES (Electrical Line Width and Sheet Resistance)
Sheet resistance and electrical line width are measured using a bridge
test structure consisting of a Van der Pauw crossed bridge for sheet
resistance measurement and a Kelvin line width measurement section.
The Van der Pauw section is the classic four-arm structure used in the
industry for many years, with arm widths of 25 µm. The tap
distances on the wire width section are determined by the design rule
wire pitch. The wire width section has a width equal to 2 * (minimum
wire width) + (minimum wire spacing). The sheet resistance-line width
bridges occupy four pad pairs and are constructed in every conducting
layer in a technology.
See
Figure 2: Sample Sheet Resistance Line Width Bridge (Metal1)
2.2.1 TESTING
Testing consists of two parts taken in the order: Van der Pauw (Rs); wire width. The Van der Pauw test is performed first because the sheet resistance obtained from this portion of the test is used in the wire width determination.
The Van der Pauw measurement is done by passing constant current through two adjacent arms of the crossed bridge and measuring voltage on diagonal pairs of arms. The measurement is repeated with the pairs of arms for current force and for voltage sense rotated 90 degrees on the crossed bridge. The two voltage readings are averaged to remove any asymmetry in the bridge.
Wire width measurements are taken by passing constant current through
the entire length of the structure and measuring the voltage between
the taps on the wire.
Sheet resistance is computed from:
RS = (pi/ln 2) * (AVG_VMEASURE / IFORCE) ohms/square
where
AVG_VMEASURE = (VMEASURE1 + VMEASURE2) / 2
pi = 3.1415927
ln is the natural logarithm
IFORCE =
The line width is computed from:
Weff = (RS * L) / (VB / IFORCE) µm
where
L = drawn wire bridge tap spacing (120 µm)
VB = measured wire bridge tap voltage
IFORCE =
Width Error is computed as follows:
W_error = W - W_drawn,
where
W_drawn is as indicated in the text above.
Sheet resistance and line width computations are carried out in the MOSIS wafer electrical test report generator rather than at probe time.
2.3 STEP COVERAGE TEST STRUCTURE
The step coverage test structure monitors metal coverage over topology steps through wire continuity and comb isolation. The structure is intended to be used to detect major process failures. In general there are not likely to be many failures due to poor metal step coverage on a structure of such a small area.
The step coverage structures can include: Poly, Metal1, Metal2,
Metal3, and Metal4. The Poly geometry consists of serpentine
polysilicon between interdigitated fingers of Poly running over oxide
steps of active area at minimum design rule width and spacing. The
Metal1 geometry consists of Metal1 over Poly and Active. The Metal2
geometry has Metal2 over Metal1, Poly, and Active. Metal3 and Metal4
geometry continue this pattern. The structures are usually paired,
where each portion of the structure occupies half of the available
space.
See
Figure 3: Sample Step Coverage (Metal 2 - Metal 3)
2.3.1 TESTING
Testing the step coverage structure involves measuring the serpentine structure for continuity and measuring the interdigitated structures for electrical shorts.
The continuity test consists of current (IFORCE = 10 mA) forced through the serpentine with a voltage measurement to calculate a resistance. Note that an open circuit in the serpentine is easily detected by setting a voltage compliance limit on IFORCE and observing if the voltage limit is reached. Electrical shorts in the interdigitated structures are detected by applying a voltage (VFORCE = process Vdd) between the serpentine and the comb and measuring the resulting current.
The parametric tester logs the voltage for the continuity test and the current for the short test. At this time the wafer electrical test summary report includes only the measured current.
2.4 THIN OXIDE TRANSISTOR STRUCTURES (N and P)
The test transistors are organized in several groups, generally along the lines of variable length, fixed width; fixed length, variable width; and others. Transistor channel geometries are listed by test vehicle in the appendix and are generated in both N channel and P channel.
These sizes are intended for use in full characterization of the
transistor process targets and for extraction of device model
parameters. A selected subset of transistor sizes makes up the minimum
set of transistors necessary for wafer acceptance. The closed
(edgeless) device is intended for evaluation of radiation hardness.
See:
Figure 4: Sample (N Enhancement) Common Transistor(s)
Figure 5: Sample (N Enhancement) Isolated Transistor(s)
2.4.1 TESTING
2.4.1.1 Tests performed on transistors are:
TRANSISTOR THRESHOLD VOLTAGE
Threshold voltages (Vth) are obtained from a conductivity curve which
is a plot of drain current versus gate voltage for a drain voltage
that is much less than twice the Fermi potential (2 * phi). The
absolute drain voltage is set at 50 mv. Threshold voltage is found by
extrapolating the linear portion of the conductivity curve to Ids = 0.
The intersection of the extrapolated line is defined as the threshold
voltage. Measurements are made using at least three different body
voltages (0, Vdd/2, and Vdd).
PROCESS GAIN FACTOR
The slope of the conduction curve obtained in the threshold voltage
measurement process is used to calculate the process gain factor
(K') The slope (S) of the conduction curve is 2 * K * Vd. Therefore,
K = S / (2 * Vd).
Since K = K'* (W / L), then the process gain factor is calculated from K' =(S/(2*Vd))*(L/W).
(Note: W and L must be corrected for as-fabricated W and L, where W = W_drawn - DW, and L = L_drawn - DL.
Derivation of W (effective) and L (effective) is discussed in the EFFECTIVE CHANNEL WIDTH/LENGTH section of this document.)
BODY EFFECT
The change in voltage threshold due to source-to-substrate (body)
reverse bias is obtained from measurements of voltage threshold at
different body reverse biases. Threshold voltages are measured at
three different body voltages (0, Vdd/2, Vdd; negative relative to
source for N channel devices and positive relative to source for the P
channel devices). Threshold voltages are measured in the manner
described above.
GAMMA (SPICE Body Effect Parameter) is assumed to be defined by
the SPICE body effect relationship:
Vt = Vt(0) + GAMMA*{SQRT(ABS(Vsb) + 2*PHI_F) SQRT(2*PHI_F)}
Taking two threshold measurements at different body voltages,
GAMMA can be calculated by taking the difference between the two
measured threshold voltages and solving for GAMMA:
GAMMA = [ABS(Vt(2)) ABS(Vt(1))] / D
where,
D = SQRT{ABS(Vsb(2)) + 2*PHI_F} SQRT{ABS(Vsb(1)) + 2*PHI_F},
and
2*PHI_F is assumed to be 0.7 for silicon technologies.
SATURATION CURRENT
Saturation current is measured by connecting the gate to the drain
(body connected to source) and applying Vgs = Vds = process Vdd and
measuring current (Idss).
PUNCH-THROUGH VOLTAGE
This test is performed on short channel devices. The punch-through
voltage is measured by using a ramp search method in which an applied
drain voltage (10 V maximum) is increased monotonically while
monitoring the drain current. The ramp voltage is logged as
punch-through voltage (Vpt) when a specified drain current flows (10
nA per µm channel width). The drain is connected to a voltage
supply (Vds) which is in series with a current meter; gate, source and
bulk are connected to ground.
As a further check, the gate and source are left open while a current
meter is connected between the bulk and ground. The same ramp test is
performed to determine if the measured Vpt actually represents
junction breakdown.
2.4.1.2 Tests performed on selected transistors include:
TRANSISTOR I/V CURVES
A selected set of transistors will be used to collect I/V curves for
SPICE model parameters. Drain current (Ids) measurements will be made
at various drain-source voltages (Vds), gate-source voltages (Vgs) and
bulk-source voltages (Vbs). The specific set of transistor geometries
and sets of bias voltages will be determined by the requirements of
the parameter extractor. The temperature of the vacuum chuck at the
time of the test is logged in the measurement data file.
ACTIVE AREA JUNCTION LEAKAGE
Junction leakage current is measured at a junction potential of
process Vdd. Source/drain-to-well junction leakage is measured with
the well connected to the bulk. Junction leakage is measured on the
drain of large, square transistor with the gate and source
floating. For increased sensitivity, junction leakage current can be
measured on the junction capacitor structures.
ACTIVE AREA JUNCTION BREAKDOWN
Junction breakdown is measured by applying a reverse bias current of
1.0 µA (positive for N junctions and negative for P junctions)
and measuring the resulting junction voltage. Source/drain-to-well
junction breakdown is measured with the well connected to the bulk.
Measurements are made on a large, square transistor using the drain
junction with the source and gate floating.
DRAIN/SOURCE LEAKAGE
Measurements are made with the gate connected to the source and a
picoammeter connected between source and ground; bulk is connected to
a specified Vbs (currently 0 V). The transistor used in this
measurement should a transistor with minimum design rule channel
length and with the largest channel width included within the process
monitor. Leakage current measurements are then normalized per
micrometer of channel width.
EFFECTIVE CHANNEL WIDTH/LENGTH
Effective channel width and length are extracted by extrapolation of
the measured channel conductance to find delta W and delta L. Values
for effective channel length and width are obtained by adding the
delta length and delta width values to the drawn length and width.
Equations are given here for extracting delta W and delta L from
measurements on two devices, but in practice a larger array of devices
with varying widths (fixed length) and varying lengths (fixed width)
is used. A linear fit to the data (S versus W, 1/S versus L) is
achieved by the method of least squares, and the W and L offsets are
obtained from the x-intercept of the function.
Delta Channel Length: DL = (L1*S1 L2*S2) / (S1 S2),
for transistors with: W1 = W2
Delta Channel Width: DW = (W1*S2 W2*S1) / (S2S1),
for transistors with: L1 = L2
where
S1 = linear region slope of the larger device
S2 = linear region slope of the smaller device
L1 = drawn device length, larger device
L2 = drawn device length, smaller device
W1 = drawn device width , larger device
W2 = drawn device width, smaller device
Note:
L_effective = L_drawn - DL
W_effective = W_drawn - DW
2.5 THICK (FIELD) OXIDE TRANSISTORS
Thick oxide transistors consist of minimum active to active regions with the gap between them covered by Metal1, Metal2 or Poly. In addition, a thick oxide transistor may be constructed with P-well (or N-well) to P+ regions (or N+ regions) at minimum spacing, covered by Metal1, Metal2, or Poly. In this test device the P-well is the source.
See
Figure 6: N_ACT/P_ACT Field Oxide Transistor Pair
2.5.1 TESTING
The threshold of the thick oxide devices is measured by using a search method in which an applied gate voltage is found such that a specified drain current flows. The drain is connected to a specified voltage (process Vdd), the source is connected to a current meter, and the bulk is connected to ground. A separate gate supply is connected to the gate terminal. The gate supply voltage is varied in a binary search pattern to find the gate voltage that will cause the drain current to be 1.0 µA. The resulting gate voltage is reported as the threshold.
2.6 VARIABLE RATIO INVERTERS
Inverters constructed with minimum channel length P- and N-channel transistors are contained in a group with common Vdd, ground, and input connections, separate outputs, and with width ratios of 1.0, 1.5, 2.0.
See Figure 7: Test Inverter(s)
2.6.1 TESTING
Each inverter is tested with Vdd set at the nominal operating voltage for the technology. The output voltage is measured with the input connected to Vdd and ground and with the output connected to a 100 µA constant current load. Vout,high is measured with 100 µA to ground. Vout,low is measured with 100 µA to Vdd. The input is connected to the output and the resulting stable voltage is identified as the inverter threshold (Vinv). Finally the gain of the inverter is measured at an input voltage of Vinv.
3.0 AC Parametric Test Structures
At present, the only AC parameters monitored are the interlayer capacitances. Transistor small signal characteristics may be monitored in the future.
The capacitor array consists of area capacitors (small perimeter), fringe capacitors (large perimeter), and gate overlap capacitors. For each capacitance reported, the capacitance measurements require data reduction to produce the desired information (e.g., extraction of the area and fringe components of capacitance). This data reduction is done in the MOSIS report generator.
All capacitors are designed to fit into the 2 x 10 pad block height of 240 µm. The lengths of the capacitor structures may be varied to obtain the desired capacitance, but are currently fixed at 300 µm. A full four point electrical structure is maintained to maximize the accuracy available from a general purpose LCR meter.
Capacitors that have one electrode connected to the well (either P-well or N-well) have a substrate-to-well strap to assure that the stray capacitance can be compensated by a null capacitor.
3.1 NULL CAPACITORS (Calibration Capacitors)
Three six-pad null capacitors are used for measuring the stray capacitances associated with the test environment (fixture plus probe pads and test structure interconnects), which are subtracted from each raw measured capacitance value during data processing.
The floating calibration capacitor measures stray capacitance associated with capacitors which have neither electrode connected to the substrate (e.g., a Metal2 to Metal1 capacitor).
One electrode of the substrate-connected calibration capacitor is connected to the substrate to measure stray capacitance associated with capacitors that use the substrate as one electrode (e.g., Metal2 to substrate).
The shield-substrate calibration capacitor connects the LCR meter cable shields to the wafer substrate in order to remove the effective substrate-connected parasitic capacitance associated with gate overlap, net-to-net, and crossover capacitors.
See Figure 8: Sample Calibration Capacitor (Floating)
3.2 AREA CAPACITORS
The area capacitors are designed with the top electrode dimensions set at 240 µm high by 300 µm wide. This provides at least 2.0 pF capacitance from the field oxide capacitors.
See Figure 9: Sample Area Capacitor (POLY to P_PLUS_ACTIVE)
3.2.1 TESTING
Measurements are made with an AC test voltage of 100 mV rms and a
frequency of 100 KHz.
Thin oxide capacitor measurements for determining gate oxide thickness
are taken in both strong inversion and accumulation of the oxide
semiconductor interface (V_gate = process Vdd). The value taken from
the measurement in strong inversion is normally used for modeling and
other applications.
All other capacitors are tested at zero bias voltage. (Modeling data
sets include C-V data for both gate and junction capacitors.)
Geometrical parameters are:
Area: Aa = H * L µm2
Perimeter: Pa = (2 * H) + (2 * L) µm
where
H = top electrode height
L = top electrode length
Thin oxide capacitor measurements are used in the computation
of the oxide thickness with the following equation:
Tox = (Aa * 3.45E-11) / Cam
where
Cam = measured capacitance of the area capacitor
3.45E-11 = permittivity of silicon dioxide
Interlayer dielectric capacitance measurements can be used to
calculate the thickness of the insulator by using the above equation
if the interlayer dielectric is silicon dioxide (dielectric constant =
3.9). If the dielectric is some other material (e.g., silicon nitride
or a combination of silicon dioxide and silicon nitride) the more
general form of the equation must be used:
Tins = Er * E0 * (Aa / Cam)
where
Er = relative dielectric constant of the insulator
E0 = permittivity of free space = 8.854E-12 farads/meter
3.3 FRINGE CAPACITORS
The fringe capacitors are comb structures with a comb width of 10 µm and a comb spacing of 10 µm. The height is slightly smaller than 240 µm, the maximum height permitted by the capacitor structures. Top electrode length is 300 µm.
See Figure 10: Sample Fringe Capacitor (P_PLUS_ACTIVE to N_WELL)
3.3.1 TESTING
Measurements are made with an AC test voltage of 100 mV rms and a
frequency of 100 KHz.
Capacitors with thin oxide between the layers are measured at zero
volts bias and with LCR meter shields connected to the substrate to
obtain the gate overlap capacitance.
All other capacitors are tested at zero bias voltage. (Modeling data
sets include C-V data for both gate and junction capacitors.)
Geometrical parameters are:
Area: Af = (NR * H * 10) + ((NR - 1) * 10 * 10) µm2
Perimeter: Pf = (H * 2) + (NR * 2 * 10) + ((NR - 1) * 2 * H) µm
where
NR = INT( L / 20 )
H = top electrode height
L = top electrode length
Computation of component capacitances (e.g., junction: CJSW and
CJ) using the area capacitor measurements and the fringe capacitor
measurements is carried with the following equations:
Fringe capacitance:
Cf = ((Cam/Aa) - (Cfm/Af)) / ((Pa/Aa) - (Pf/Af)) aF/µm
Area capacitance:
Ca = (Cam/Aa) - Cf * (Pa/Aa) aF/µm2
where
Cam = measured capacitance of the area capacitor
Cfm = measured capacitance of the fringe capacitor
4.0 Functional Test Structures
The functional test structures are used to evaluate the performance of the extracted model parameters and to act as an alarm for a low yield wafer lot.
The functional test area is configured so that the pinout is
standardized to minimize the complexity of the interface to test
equipment. This pinout is defined assuming the following pin
numbering convention:
See
Figure 11: Functional Test Area
The Input/Output pins and the Clock are interfaced with tri-state I/O
pins on the functional tester. Pin 12 is also connected to a small
relay that can connect the ring oscillator ENABLE signal to this
pin. The purpose of the relay is to reduce the stray capacitance
associated with the ENABLE signal wire.
4.1 RING OSCILLATOR
The Ring Oscillator in the MOSIS process Monitor is used to serve as a very simple benchmark performance measure of the various foundry technologies supported by MOSIS. It also serves as one of the functional devices for verifying the accuracy of circuit simulations that use the MOSIS extracted SPICE model parameters.
By simulating a design using MOSIS model parameters from several wafer lots, a design can be tested for performance over past fabricated lots. Since typical foundries are fairly stable, then simulations using past history are useful for providing an estimate of what performance to expect in future wafer lots. Model parameters for each wafer lot are tested by simulating inverter and ring oscillator circuits fabricated in the MOSIS process monitor on each wafer lot. The simulation versus measured error must be less than 10% to have the model parameters be acceptable for MOSIS to post them in the wafer lot Parametric Test Results. If the model parameters fail to meet this requirement, then the measured I-V data is re-analyzed (or new data is collected) and a new set of model parameters are optimized and tested as indicated above.
The Ring Oscillator consists of a string of 31 simple inverters that form the ring oscillator. No attempt is made to construct the ring oscillator using one of the many cell library inverters or gates. The layout is intentionally very compact to cause the ring oscillator frequency performance to be dominated by the transistors. Device channel lengths used for ring oscillator are minimum design rule channel length, which is (2 * lambda). The standard width for NMOS device is (4 * lambda) and (8 * lambda) for PMOS. One inverter stage of the ring oscillator is replaced with a 2-input NAND gate, which serves as an externally controlled trigger to prevent multi-mode oscillation from occurring during power-up. The ring oscillator output is isolated with a buffer and then is connected to a divide by 256 counter (or a 1024 counter for 0.25 µm technology and smaller) to reduce the output frequency. Reducing the output frequency permits using the parametric test system pin matrix, directing the ring oscillator frequency divided output to a frequency counter during wafer probe. The output of the frequency divider is buffered for output onto a highly capacitance loaded measuring system. Frequency measurements from the frequency counter are multiplied by the above counter stage size in order to report the actual 31- stage ring oscillator frequency in the MOSIS Parametric Test Results.
The ring oscillator layout is configured to separate the power supply for the 31-stage ring oscillator from the divider/output buffer so we are able to obtain accurate power measurements. The measured ring oscillator frequency obtained in the manner above, along with the power supply current to the 31-stage ring oscillator is used to calculate the reported per stage power in uw/MHz/gate.
In some technologies, a second ring oscillator will be added to the MOSIS Process Monitor in order to measure the performance of different transistor types (such as the thick gate oxide option from TSMC) or to assess the effects of channel narrowing (such as in the AMI C5N 0.5 µm). In the case of the C5N (0.5 µm), the transistors in the inverters are (10 * lambda) width for NMOS and (20 * lambda) width for PMOS (L is still 2 lambda). The ring oscillator frequency and power using these larger width devices is higher than the standard width devices. This difference is because the effect of channel narrowing is a smaller percentage of the layout width and because the wider devices can drive larger current to overcome the effects of the small parasitic capacitance external to the transistors.
See Figure 12: Sample Ring Oscillator (Inverter)
4.1.1 TESTING
The parametric tester supplies power (Vdd and ground) to the device under test through the probe card interface board. A relay is activated to connect a parametric tester pin to the ring oscillator enable pin and a disable voltage level is applied to suppress any multimode oscillation that may be present. The disable voltage is removed to start oscillation and a frequency measurement is taken.
The parametric test system reports the average of two consecutive frequency measurements in which the second reading is within 10% of the first. Up to five readings are taken until the above condition is achieved. If acceptable readings are not found then the structure is considered inoperative.
4.2 YIELD MONITOR
The yield monitor is a set of n-element shift registers where n is determined by the MOSIS test layout generator and is a function of the total area allocated to the circuit. Current designs have either 10 or 14 channels, each with n elements.
4.2.1 TESTING
Yield monitor testing is performed with a functional tester that operates independently from the parametric tester. The functional tester supplies power (Vdd and ground) to the device under test through the probe card interface board. A device is considered functional if it passes (shifts) logic 1 and logic 0 inputs on each channel to the outputs after an appropriate number of clock cycles.
5.0 Test Structure Identification
MOSIS process monitor test structure layouts include a reference designator to help locate a particular structure within the process monitor. The following tables list the test structure names and their corresponding reference designators.
| Capacitors | Test Block Title | Designator | Notes | |
|---|---|---|---|---|
| Crossover Capacitor METAL2 to METAL1 | C1 | Not used | ||
| Crossover Capacitor METAL 1 to POLY | C2 | Not used | ||
| Edge Capacitor POLY to POLY | C3 | Not used | ||
| Edge Capacitor METAL2 to METAL2 | C4 | Not used | ||
| Edge Capacitor METAL1 to METAL1 | C5 | Not used | ||
| Fringe Capacitor POLY to N_PLUS_ACTIVE | C6 | |||
| Fringe Capacitor POLY to P_PLUS_ACTIVE | C7 | |||
| Fringe Capacitor N_PLUS_ACTIVE to P_WELL | C8 | |||
| Fringe Capacitor P_PLUS_ACTIVE to N_WELL | C9 | |||
| Area Capacitor METAL2 to POLY | C10 | |||
| Area Capacitor METAL1 to POLY | C11 | |||
| Area Capacitor METAL2 to METAL1 | C12 | |||
| Area Capacitor METAL2 to N_PLUS_ACTIVE | C13 | |||
| Area Capacitor METAL1 to N_PLUS_ACTIVE | C14 | |||
| Area Capacitor METAL2 to N_WELL | C15 | |||
| Area Capacitor METAL1 to N_WELL | C16 | |||
| Area Capacitor POLY to N_WELL | C17 | |||
| Area Capacitor N_PLUS_ACTIVE to P_WELL | C18 | |||
| Area Capacitor P_PLUS_ACTIVE to N_WELL | C19 | |||
| Area Capacitor POLY to N_PLUS_ACTIVE | C20 | |||
| Area Capacitor POLY to P_PLUS_ACTIVE | C21 | |||
| Calibration Capacitor with connected substrate | C22 | |||
| Calibration Capacitor floating | C23 | |||
| Area Capacitor ELECTRODE* to POLY | C30 | * Second Poly | ||
| Area Capacitor METAL1 to ELECTRODE* | C31 | |||
| Area Capacitor METAL2 to ELECTRODE* | C32 | |||
| Area Capacitor ELECTRODE* to N_PLUS_ACTIVE | C33 | |||
| Area Capacitor ELECTRODE* to P_PLUS_ACTIVE | C34 | |||
| Area Capacitor ELECTRODE* to P_WELL | C35 | |||
| Fringe Capacitor ELECTRODE* to N_PLUS_ACTIVE | C36 | |||
| Fringe Capacitor ELECTRODE* to P_PLUS_ACTIVE | C37 | |||
| Edge Capacitor ELECTRODE* to ELECTRODE* | C38 | Not used | ||
| Fringe Capacitor METAL1 to P_WELL | C39 | |||
| Fringe Capacitor METAL2 to P_WELL | C40 | |||
| Fringe Capacitor METAL1 to POLY | C41 | |||
| Fringe Capacitor METAL2 to POLY | C42 | |||
| Area Capacitor METAL3 to P_WELL | C43 | |||
| Area Capacitor METAL3 to N_PLUS_ACTIVE | C44 | |||
| Area Capacitor METAL3 to METAL2 | C45 | |||
| Area Capacitor METAL3 to POLY | C46 | |||
| Fringe Capacitor METAL3 to P_WELL | C47 | |||
| Fringe Capacitor METAL3 to POLY | C48 | |||
| Edge Capacitor METAL3 to METAL3 | C49 | Not used | ||
| Crossover Capacitor METAL3 to METAL2 | C50 | Not used | ||
| Fringe Capacitor POLY to P_WELL | C51 | |||
| Fringe Capacitor ELECTRODE* to P_WELL | C52 | |||
| Fringe Capacitor METAL1 to N_PLUS_ACTIVE | C53 | |||
| Fringe Capacitor METAL2 to N_PLUS_ACTIVE | C54 | |||
| Fringe Capacitor METAL3 to N_PLUS_ACTIVE | C55 | |||
| Fringe Capacitor METAL2 to METAL1 | C56 | |||
| Fringe Capacitor ELECTRODE* to POLY | C57 | |||
| Fringe Capacitor METAL1 to ELECTRODE* | C58 | |||
| Fringe Capacitor METAL2 to ELECTRODE* | C59 | |||
| Fringe Capacitor METAL3 to METAL2 | C60 | |||
| Area Capacitor METAL3 to METAL1 | C61 | |||
| Fringe Capacitor METAL3 to METAL1 | C62 | |||
| Area Capacitor POLY to CAP_WELL** | C63 | ** HP Linear Cap | ||
| Fringe Capacitor POLY to CAP_WELL** | C64 | |||
| Area Capacitor POLY to CAP_IMPLANT** | C65 | |||
| Calibration Capacitor with connected shield | C66 |
| Functional devices | Test Block Title | Designator | Notes |
|---|---|---|---|
| Dynamic Shift Register | F1 | Not used | |
| Pattern Generator | F2 | Not used | |
| Ring Oscillator | F3 | ||
| XOR tree | F4 | Not used | |
| Ring Oscillator trio | F6 | ||
| Ring Oscillator pair | F7 | ||
| Divided-by-four Ring Oscillator | F8 | ||
| Shift Register Yield Monitor (rev 2) | F10 | ||
| Shift Register Yield Monitor (rev 4) | F11 | ||
| Inverter Ring Oscillator | F12 | ||
| Nand2 Ring Oscillator | F13 | ||
| Nor2 Ring Oscillator | F14 | ||
| Non-feature-size Ring Oscillator | F15 | ||
| Non-feature-size Divided-by-four Ring Oscillator | F16 |
| Inverters | Test Block Title | Designator | Notes |
|---|---|---|---|
| Test inverter(s) | I1 |
| Sheet and contact resistance bridges | Test Block Title | Designator | Notes |
|---|---|---|---|
| Poly (P+) bridge | K1 | ||
| Poly (N+) bridge | K2 | ||
| P+ Active bridge | K3 | ||
| N+ Active bridge | K4 | ||
| Metal bridge | K5 | ||
| Second_metal bridge | K6 | ||
| P-Well bridge | K7 | ||
| N-Well bridge | K8 | ||
| P+ Active to Metal contact | K9 | ||
| Second Metal to First Metal contact | K10 | ||
| Poly bridge | K11 | ||
| Poly (P+) to Metal contact | K12 | ||
| Poly (N+) to Metal contact | K13 | ||
| N+ Active to Metal contact | K14 | ||
| P-Well under Poly bridge | K15 | ||
| N-Well under Poly bridge | K16 | ||
| Electrode* bridge | K20 | * Second Poly | |
| Electrode* to Metal contact | K21 | * Second Poly | |
| Third Metal to Second Metal contact | K23 | ||
| Third_metal bridge | K24 | ||
| N-Ldd bridge | K25 | ||
| P-Ldd bridge | K26 | ||
| Second Metal to First Metal contact over Poly | K27 | ||
| Second Metal to First Metal contact over Active | K28 | ||
| Third Metal to Second Metal contact over Active | K29 | ||
| Third Metal to Second Metal contact over Poly | K30 | ||
| Third Metal to Second Metal contact over Metal1 | K31 | ||
| Third Metal to Second Metal contact over Poly and Metal1 | K32 | ||
| Poly (P+) to Metal contact (min overlap) | K33 | ||
| Poly (N+) to Metal contact (min overlap) | K34 | ||
| N+ Active to Metal contact (min overlap) | K35 | ||
| P+ Active to Metal contact (min overlap) | K36 | ||
| Contact string | K37 | ||
| Poly (non silicided) bridge | K38 | ||
| Poly (non silicided) to Metal contact | K39 |
| Step coverage | Test Block Title | Designator | Notes | |
|---|---|---|---|---|
| Step coverage METAL1 METAL2 | S1 | |||
| Step control METAL1 METAL2 | S2 | |||
| Step coverage METAL2 | S3 | |||
| Step control METAL2 | S4 | |||
| Step coverage METAL1 | S5 | |||
| Step control METAL1 | S6 | |||
| Step coverage METAL2 METAL3 | S7 | |||
| Step control METAL2 METAL3 | S8 | |||
| Step coverage METAL3 | S9 | |||
| Step control METAL3 | S10 | |||
| Step coverage POLY METAL1 | S11 | |||
| Step control POLY METAL1 | S12 | |||
| Step coverage POLY | S13 | |||
| Step control POLY | S14 | |||
| Poly (N/P) bridging test structure | S15 | |||
| Transistors | Test Block Title | Designator | Notes | |
| N_ENHANCEMENT common transistor(s) | T1 | |||
| P_ENHANCEMENT common transistor(s) | T2 | |||
| N_ACT field oxide transistors | T3 | |||
| P_ACT field oxide transistors | T4 | |||
| N_ENHANCEMENT isolated transistor(s) | T5 | |||
| P_ENHANCEMENT isolated transistor(s) | T6 | |||
| N_ENHANCEMENT closed transistor | T7 | |||
| P_ENHANCEMENT closed transistor | T8 | |||
| N_ACT field oxide (REVISED) transistors | T12 | |||
| P_ACT field oxide (REVISED) transistors | T13 | |||
| N_ACT / P_ACT field oxide (REVISED) transistor pair | T14 | |||
| NPN common transistor(s) | T15 | |||
| N_ACT field oxide (NEW) transistors | T16 | |||
| P_ACT field oxide (NEW) transistors | T17 | |||
| N_ACT / P_ACT field oxide (NEW) transistor pair | T18 | |||
| N_LDD_ENHANCEMENT isolated transistor(s) | T19 | |||
| P_LDD_ENHANCEMENT isolated transistor(s) | T20 | |||
| N_POLY2_ENHANCEMENT* common transistor(s) | T21 | * Second Poly | ||
| P_POLY2_ENHANCEMENT* common transistor(s) | T22 | * Second Poly | ||
| N_POLY2_ENHANCEMENT* isolated transistor(s) | T23 | * Second Poly | ||
| P_POLY2_ENHANCEMENT* isolated transistor(s) | T24 | * Second Poly |
6.0 Test Index
INTERCONNECT PARAMETERS
| Contact Resistance | Structure Designator | Test Reference Section |
|---|---|---|
| N+ Active to M1 | K14 | 2.1 |
| P+ Active to M1 | K9 | |
| Poly (N+) to M1 | K13 | |
| Poly (P+) to M1 | K12 | |
| M2 to M1 (Field) | K10 | |
| M2 to M1 (Poly) | K27 | |
| M2 to M1 (Active) | K28 | |
| M3 to M2 (Field) | K23 | |
| M3 to M2 (Poly) | K29 | |
| M3 to M2 (Active) | K30 | |
| M3 to M2 (Metal1) | K31 | |
| M3 to M2 (Poly, Metal1) | K32 | |
| Poly (P+) to M1 (Min. Overlap) | K33 | |
| Poly (N+) to M1 (Min. Overlap) | K34 | |
| N+ Active to M1 (Min. Overlap) | K35 | |
| P+ Active to M1 (Min. Overlap) | K36 | |
| Contact String | K37 | |
| Poly (non-silicided) to M1 | K39 | |
| Electrode* to M1 | K21 | * Second Poly |
| Voltage Sum (rectifying) | Structure Designator | Test Reference Section |
|---|---|---|
| N+ Active to M1 | K14 | 2.1 |
| P+ Active to M1 | K9 | |
| Poly (N+) to M1 | K13 | |
| Poly (P+) to M1 | K12 |
| Sheet Resistance | Structure Designator | Test Reference Section |
|---|---|---|
| Poly (P+) | K1 | 2.2 |
| Poly (N+) | K2 | |
| P+ Active | K3 | |
| N+ Active | K4 | |
| Metal1 | K5 | |
| Metal2 | K6 | |
| P-Well | K7 | |
| N-Well | K8 | |
| Poly | K11 | |
| P-Well under Poly | K15 | |
| N-Well under Poly | K16 | |
| Electrode* | K20 | * Second Poly |
| Metal3 | K24 | |
| N-Ldd | K25 | |
| P-Ldd | K26 | |
| Poly (non silicided) | K38 |
| Delta Line Width | Structure Designator | Test Reference Section |
|---|---|---|
| Poly (P+) | K1 | 2.2 |
| Poly (N+) | K2 | |
| P+ Active | K3 | |
| N+ Active | K4 | |
| Metal1 | K5 | |
| Metal2 | K6 | |
| P-Well | K7 | |
| N-Well | K8 | |
| Poly | K11 | |
| P-Well under Poly | K15 | |
| N-Well under Poly | K16 | |
| Electrode* | K20 | * Second Poly |
| Metal3 | K24 | |
| N-Ldd | K25 | |
| P-Ldd | K26 | |
| Poly (non silicided) | K38 |
| Step Comb Isolation | Structure Designator | Test Reference Section |
|---|---|---|
| Step coverage Metal1 Metal2 | S1 | 2.3 |
| Step control METAL1 METAL2 | S2 | |
| Step coverage METAL2 | S3 | |
| Step control METAL2 | S4 | |
| Step coverage METAL1 | S5 | |
| Step control METAL1 | S6 | |
| Step coverage METAL2 METAL3 | S7 | |
| Step control METAL2 METAL3 | S8 | |
| Step coverage METAL3 | S9 | |
| Step control METAL3 | S10 | |
| Step coverage POLY METAL1 | S11 | |
| Step control POLY METAL1 | S12 | |
| Step coverage POLY | S13 | |
| Step control POLY | S14 | |
| Poly (N/P) bridging test structure | S15 |
| Step Serpentine Continuity | Structure Designator | Test Reference Section |
|---|---|---|
| Step coverage Metal1 Metal2 | S1 | 2.3 |
| Step control METAL1 METAL2 | S2 | |
| Step coverage METAL2 | S3 | |
| Step control METAL2 | S4 | |
| Step coverage METAL1 | S5 | |
| Step control METAL1 | S6 | |
| Step coverage METAL2 METAL3 | S7 | |
| Step control METAL2 METAL3 | S8 | |
| Step coverage METAL3 | S9 | |
| Step control METAL3 | S10 | |
| Step coverage POLY METAL1 | S11 | |
| Step control POLY METAL1 | S12 | |
| Step coverage POLY | S13 | |
| Step control POLY | S14 | |
| Poly (N/P) bridging test structure | S15 |