MOSIS FAQs: Wafer Electrical Specifications
1.0 What is the site-to-site, wafer-to-wafer, lot-to-lot variation in MOSIS electrical parameters? Does MOSIS have transistor matching data?
2.0 How do I determine the maximum power dissipation of my design?
3.0 Recent wafer electrical test results for Hewlett-Packard AMOS14TB runs do not contain values for N-well sheet resistance or silicide-blocked polysilicon. Why?
4.0 Is it possible to obtain parametric data mapped to specific sites on the wafers from a given MOSIS run?
5.0 How can I obtain process characteristic data, such as temperature coefficients of resistance, that is not posted with the electrical test data for each MOSIS run?
6.0 I have detailed questions regarding a MOSIS-supported wafer fabrication process. How can I contact the foundry directly for answers to these questions?
7.0 I am accustomed to calculating an effective channel length (L_effective) according to the formula:
L_effective = L_drawn + XL - (2 * LD)
How can I derive this quantity from the MOSIS on-line SPICE BSIM3 parameters, which do not include LD?
8.0 What is the difference between a polycide and a silicide process?
1.0 What is the site-to-site, wafer-to-wafer, lot-to-lot variation in MOSIS electrical parameters? Does MOSIS have transistor matching data?
MOSIS does not have systematic data on variations within a die, including transistor matching data. An estimate of site-to-site variations within a lot and among different MOSIS lots may be obtained by examining the wafer electrical test summaries posted on the MOSIS web site.
More specific data may be available to registered MOSIS customers who request it. Requests should be submitted through the MOSIS Inquiry and Customer Support System (your email address is your user ID in that system). Please specify in reasonable detail what is needed and why it is needed, and include your MOSIS account number and password.
See also "Characterization of Subthreshold MOS Mismatch in Transistors for VLSI Systems," A. Pavasovic, A. G. Andreou, and C. R. Westgate, Journal of VLSI Signal Processing, 8, 75-85 (1994).
2.0 How do I determine the maximum power dissipation of my design?
It is not possible to provide a simple specification for power density because the power dissipated per unit area is strongly dependent upon the thermal characteristics of the package and on heat management in the system in which the IC will be used.
Wafer vendors will specify the maximum specification for junction temperature for a process, typically in the neighborhood of 85 to 125 C. The designer is responsible for determining maximum power density for this maximum junction temperature by modeling the application thermal environment.
For thermal characteristics of MOSIS-provided IC packages, select Packages Available Through MOSIS
3.0 Recent wafer electrical test results for Hewlett-Packard AMOS14TB runs do not contain values for N-well sheet resistance or silicide-blocked polysilicon. Why?
Space limitations have prevented MOSIS from fabricating the process monitor containing those test structures. The vendor's nominal values are:
| Rs, N_well | 715 ohms/square |
| Rs, non-silicided poly | 90 ohms/square |
4.0 Is it possible to obtain parametric data mapped to specific sites on the wafers from a given MOSIS run?
Vendors do not generally provide this information.
In special cases MOSIS may release to approved customers wafer-mapped data for selected parameters from the MOSIS standard nine-sites-per-wafer database.
5.0 How can I obtain process characteristic data, such as temperature coefficients of resistance, that is not posted with the electrical test data for each MOSIS run?
Information about the fabrication processes available through MOSIS can be found on our web site.
Additional process parameters may be available by special request to registered MOSIS customers. Send a message through the MOSIS Support System specifying in reasonable detail what you need and why you need it. Include your MOSIS account number and password.
See also the Fabrication Processes FAQ.
6.0 I have detailed questions regarding a MOSIS-supported wafer fabrication process. How can I contact the foundry directly for answers to these questions?
Our agreements with our vendors stipulate that all customer questions regarding design rules, electrical specifications, and other documented process information be handled by MOSIS, not by the vendor.
Instructions how to obtain information for MOSIS-supported wafer fabrication process are in the answer to question 5 above.
7.0 I am accustomed to calculating an effective channel length (L_effective) according to the formula:
L_effective = L_drawn + XL - (2 * LD)
How can I derive this quantity from the MOSIS on-line SPICE BSIM3 parameters, which do not include LD?
There are many ways to define, calculate, estimate, and measure effective MOS channel dimensions, some biased more toward physical properties of the devices and some more toward goodness of fit of a particular model.
The formula above is valid for SPICE Level 3 and similar models, but is not applicable for BSIM3v3 because BSIM3v3 does not have an LD parameter, where LD represents the portion of the source-drain active area that lies under the gate,
The simple BSIM3v3 analog of LD is LINT, which we do extract and optimize.
The formula for effective channel length with MOSIS BSIM3v3 parameters is
L_effective = L_drawn - (2 * LINT)
(For this discussion we have simplified this expression somewhat. BSIM3v3 permits several more terms. Note that XL, which is not a BSIM3 parameter, but which is recognized by some modeling tools as a mask and process geometric bias factor (see FAQ on XL, XW), does not appear in the equation because it is incorporated into LINT during parameter extraction and optimization.)
Keep in mind that a process descriptor like "0.18 micron" is an approximation of the actual physical and-or effective electrical dimensions, the precise meaning of which varies considerably from vendor to vendor and from process to process and from NMOS to PMOS devices.
Also keep in mind that values for LINT, WINT, and other model parameters may be determined as much or more by the specific extraction and optimization procedures used to produce them as they are by the physical characteristics of the devices. A small change in a parameter optimization strategy can produce relatively large changes in LINT, for example, while still resulting in an overall set of model parameters that fits reasonably well.
In other words, you cannot properly interpret LINT, or the L_effective calculated from it, without considering the entire measurement process and extraction and optimization procedures that produced it.
8.0 What is the difference between a polycide and a silicide process?
Silicidization is the process of forming a surface layer of a refractory metal silicide on silicon. A metal, typically today titanium or cobalt, is deposited on the silicon (gate polysilicon and-or source drain regions), and a layer of silicide is formed when the two substances react at elevated temperatures.
Why do it? To lower the resistance of the polysilicon interconnect and-or the source-drain contact and sheet resistances.
In a "polycide" process only the polysilicon is silicided.
In a "silicide" process (usually implemented as a self-aligned silicidization - from whence the term "salicide") both gate polysilicon and source-drain regions are silicided.
Some processes provide a silicide blocking mask so that resistors can be constructed from the higher-resistance non-silicided material.