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SPICE Model Parameters for Submicron Technologies
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BSIM3V3:
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MOSIS now provides SPICE BSIM3v3 parameters for all MOSIS
sub-micrometer CMOS technologies. Parameters extracted and optimized
for each CMOS fabrication run processed through MOSIS are available
on the
SPICE Model Parameters
page of the MOSIS web site.
BSIM3v3, which has been adopted widely throughout the semiconductor
industry, explicitly incorporates short and narrow channel, graded
junction, and poly depletion effects, with performance in the
subthreshold and transition regions superior to that of earlier
models. Many BSIM3v3 parameters are linked to physical device
characteristics, and with only a few binning parameters it is possible
to simulate with reasonable accuracy a wide range of device sizes.
MOSIS will continue to publish lot-specific SPICE Level 3 parameters
for technologies with feature sizes 1.0 micrometer and larger.
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Limitations of Level 3:
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MOSIS has conducted performance comparisons to determine the best
strategy for extracting SPICE model parameters for technologies with
feature sizes below one micrometer. The Level 3 MOSFET model was
originally developed for channel lengths and widths less than 2.0 um,
and this model has performed adequately for classical abrupt-junction
source and drain at geometries down to about 1.0 um. However, because
of limitations in commercially supported SPICE software, we have
experienced difficulty in fitting Level 3 SPICE model parameters to
the performance of devices fabricated with submicron geometries.
We summarize here the problems we have encountered when attempting to
model Hewlett Packard's 0.8 um process with SPICE Level 3. A more
detailed discussion is contained in the attached appendix (with
references). General discussions of known Level 3 model problems may
be found in references [1, 2].
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The conventional Level 3 model will not provide subthreshold
current modeling without the NFS parameter. Ids anomalies will usually
occur in the transition between the subthreshold and linear regions.
HSPICE has a better custom subthreshold Ids model, but we do not use
it in order to maintain compatibility with the Berkeley Level 3 model.
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The conventional Level 3 model does not have a channel width
correction factor (WD, or DW in HSPICE). We carry out extractions with
*adjusted* transistor widths and have added the following comments in
the parameter file in order to supply the information needed for the
correction:
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Weff = Wdrawn - Delta_W
The suggested Delta_W is 5.6820E-07
It is the user's responsibility to extract their SPICE netlist with
this channel width correction in mind.
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Known modeling discontinuities: Modeling errors in output
conductance (gds) at Vds = Vsat and transconductance (gm) at Vgs = Vth
may cause inaccurate simulations for analog circuits and increase the
probability of run-time non-convergence.
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Charge conservation problem [2,3]: Even though HSPICE has a
supplementary gate capacitance model which is charge conserving, MOSIS
does not use it in order to maintain Berkeley model compatibility.
The BSIM3v3 model circumvents many of the difficulties associated with
Level 3. To improve AC and DC simulation accuracy, and in line with
the general direction of the industry, MOSIS now supplies BSIM3v3
parameters for submicron technologies.
Particular emphasis will be placed on gm tracking over bias in the
linear and saturation regions, and on capacitance modeling parameters
that have significant effects on AC simulations.
For these reasons, and for those outlined in the Appendix and
References below, MOSIS encourages designers to begin making a
transition away from Level 3 model parameters.
APPENDIX
Level 3 Model Parameter Model Behavioral Problems in Submicron CMOS.
Before exploring the Level 3 model problem for submicron
technologies, the following brief review of the Level 3 threshold
voltage and drain current equations [4] may be useful.
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Ids = Beta * [Vgs - Vth - (1 + fb)*Vds/2] * Vds,
where fb is a correction factor required for short channel effects
(parameter fs) and narrow channel width effects (parameter fn) and can
be written as:
gamma * fs
fb = --------------------------- + fn.
4*(Vphi - Vbs)^0.5
These two correction parameters, fs and fn, are also present in the
threshold voltage (Vth) expression as follows:
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Vth = Vfb + Vphi - sigma * Vds + gamma * fs * (Vphi - Vbs)^0.5
+ fn * (Vphi - Vbs).
>
The equations for fs and fn are complicated; references [2] and [4]
provide details. The expressions are obtained by Deng's refined model
[5] based upon Yau's two-dimensional analytical results in [6], and
are based on physical parameters such as channel length reduction,
junction depth and depletion width. Empirical constants obtained by
data fitting are also involved.
Assumptions underlying the derivation of the Level 3 correction terms
fs and fn for submicron technologies are generally *not* valid
because of advanced fabrication processes such as LDD (lightly doped
drain) and vertical channel engineering [7,8]. This is true for both
steady-state and transient behavior.
The result of this difference between model equations and reality is
that optimization for an accurate fit between measured and modeled
behavior produces unreasonable physical values for most extracted
parameters. On the other hand, if model parameter values are
restricted to a "meaningful" physical region, the accuracy of the
simulation will be compromised. Similar tradeoffs arise between
different regions of operation (e.g., linear vs. saturation).
This problem is exacerbated by mask compensation requirements, which
result in a difference between drawn gate length (at the CIF level)
and actual gate length at the chip level. This scaling is not only
required by designs rendered in MOSIS SCMOS rules, but also with
designs rendered in HP rules. This results in non-physical correction
terms, fn and fs, and leads to further inaccuracies in transistor
simulations.
It was possible to minimize these types of errors in HP's 1.2
micrometer process, but this is no longer the case for the 0.8
micrometer process. It has become difficult or impossible to get a
reasonably good set of SPICE Level 3 model parameters for the 0.8
micrometer process.
REFERENCES
[1] Y. P. Tsividis and K. Suyama, MOSFET Modeling for Analog Circuit
CAD: Problems and Prospects, IEEE JSSC, 1994. Volume 29, number
3, pages 210--216.
[2] HSPICE User's Manual, Meta-Software, Inc., HSPICE version H92,
1992.
[3] D. E. Ward and R. W. Dutton, A Charge-Oriented Model for {MOS}
Transient Capacitances, IEEE JSSC, 1978. Volume SC-13, number 4,
pages 703--707.
[4] A. Vladimirescu and S. Liu, The Simulation of MOS Integrated
Circuits Using SPICE2, Electronics Research Laboratory, UC
Berkeley, 1980. UCB/ERL M80/7.
[5] L. M. Deng, A Simple Current Model for Short-Channel IGFET and
Its Application to Circuit Simulation, IEEE JSSC, 1979. Volume
SC-14, number 2, pages 358--367.
[6] L. D. Yau, A Simple Theory to Predict the Threshold Voltage of
Short-Channel IGFETs, Solid-State Electronics, 1974. Volume 17,
pages 1059--1063.
[7] E. Adler et al., The Evolution of {IBM CMOS DRAM} technology,
IBMJ, 1995. Volume 39, number 1/2, pages 167--188.
[8] C. W. Koburger III et al., A Half-Micron CMOS Logic Generation,
IBMJ, 1995. Volume 39, number 1/2, pages 215--227.
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