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TSMC Layer Map
TSMC18
This is the layer map for the TSMC 0.18 micron 6 metal, 1 poly
(silicided) layout rules (TSMC18), and only for those TSMC
vendor design rules. For designs that are laid out using other design
rules (or
technology codes),
use the standard layer mapping conventions of that design rule set.
|
Layer
|
GDS
|
CIF
|
Notes
|
|
Layer
|
Datatype
|
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N_WELL
|
2
|
0
|
T02
|
|
|
DEEP_NWELL
|
82
|
0
|
T82
|
Optional
|
|
THIN_OXIDE (OD)
|
3, 11, 12
|
0
|
T03, T11, T12
|
|
|
THICK_OXIDE (OD2)
|
4
|
0
|
T04
|
Optional
|
|
POLY
|
13
|
0
|
T13
|
|
|
RPO
|
34
|
0
|
T34
|
Optional
|
|
2VN
|
61
|
0
|
T61
|
Derived from NP, OD2, N_Well when 2VN is completely absent from
layout. See Note #3
|
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3VN
|
5
|
0
|
T05
|
Derived from NP, OD2, N_Well when 3VN is completely absent from
layout. See Note #3
|
2VP
|
35
|
0
|
T35
|
Derived from PP, OD2, N_Well when 2VP is completely absent from
layout. See Note #3
|
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3VP
|
140
|
0
|
T140
|
Derived from PP, OD2, N_Well when 3VP is completely absent from
layout. See Note #3
|
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NT_N
|
129
|
0
|
T129
|
Optional
|
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P_PLUS_SELECT (PP)
|
7
|
0
|
T07
|
|
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N_PLUS_SELECT (NP)
|
8
|
0
|
T08
|
|
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ESD_3V
|
30
|
0
|
T30
|
Obsolete
|
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CONTACT
|
15
|
0
|
T15
|
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METAL1
|
16
|
0
|
T16
|
|
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METAL1_FILL
|
16
|
1
|
T16F
|
See Note #1
|
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METAL1_SLOT
|
16
|
2
|
T16S
|
See Note #1
|
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VIA
|
17
|
0
|
T17
|
|
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METAL2
|
18
|
0
|
T18
|
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METAL2_FILL
|
18
|
1
|
T18F
|
See Note #1
|
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METAL2_SLOT
|
18
|
2
|
T18S
|
See Note #1
|
|
VIA2
|
27
|
0
|
T27
|
|
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METAL3
|
28
|
0
|
T28
|
|
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METAL3_FILL
|
28
|
1
|
T28F
|
See Note #1
|
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METAL3_SLOT
|
28
|
2
|
T28S
|
See Note #1
|
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VIA3
|
29
|
0
|
T29
|
|
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METAL4
|
31
|
0
|
T31
|
|
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METAL4_FILL
|
31
|
1
|
T31F
|
See Note #1
|
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METAL4_SLOT
|
31
|
2
|
T31S
|
See Note #1
|
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VIA4
|
32
|
0
|
T32
|
|
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METAL5
|
33
|
0
|
T33
|
|
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METAL5_FILL
|
33
|
1
|
T33F
|
See Note #1
|
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METAL5_SLOT
|
33
|
2
|
T33S
|
See Note #1
|
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CAP_TOP_METAL
|
67
|
5
|
T67
|
Optional; see Note #2
|
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VIA5
|
39
|
0
|
T39
|
|
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METAL6
|
38
|
0
|
T38
|
|
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METAL6_FILL
|
38
|
1
|
T38F
|
See Note #1
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METAL6_SLOT
|
38
|
2
|
T38S
|
See Note #1
|
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VARDUMMY
|
138
|
0
|
T138
|
Optional
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DMN2V
|
184
|
0
|
T184
|
Optional
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DMP2V
|
149
|
0
|
T149
|
Optional
|
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ESD3DMY
|
234
|
0
|
T234
|
Optional
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RLPPDMY
|
134
|
0
|
T134
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Optional
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HRI
|
48
|
0
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T48
|
Optional
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GLASS
|
19
|
0
|
T19
|
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Note #1:
MOSIS recognizes and process these optional metal fill and slot layers,
beginning with runs closing in July, 2003.
Note #2:
This layer, which forms a MiM capacitor with METAL5 as the bottom layer,
is the standard MiM for MOSIS MPW runs. Other CTM layers, which use different
bottom plates, are also available, but only by special order. The GDS
datatype indicates the bottom metal layer that is intended.
Note #3:
If this layer is present anywhere in the submitted design or anywhere
in the design after instantiation, then MOSIS will not derive it. If
this layer is not in the submitted design or anywhere in the design
after instantiation, then MOSIS will derive that layer from the listed
layers. MOSIS does not create a layer partially from a layer drawn by
the customer and partially derived from other layers.
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