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MOSIS SCMOS Technology Codes and Layer Maps
SCN5M, SCN5M_SUBM, and SCN5M_DEEP

This is the layer map for the technology codes SCN5M_SUBM and SCN5M_DEEP using the MOSIS Scalable CMOS layout rules ( SCMOS), and only for SCN5M_SUBM and SCN5M_DEEP. For designs that are laid out using other design rules (or technology-codes), use the standard layer mapping conventions of that design rule set. For submissions in GDS format, the datatype is "0" (zero) unless specified in the map below.

SCN5M_SUBM: Scalable CMOS N-well, 5 metal, 1 poly, thick oxide option, and supports silicide block. MiM (Cap_Top_Metal, also known as Metal 4 Prime, to Metal 4) capacitors are available. Uses revised layout rules for better fit to sub-micron processes (see section 2.4)

SCN5M_DEEP: Uses revised layout rules for better fit to deep sub-micron processes (see section 2.4)

Fabricated on TSMC 0.25 micron process runs.

Layer GDS CIF CIF Synonym Rule
Section
Notes
N_WELL 42 CWN   1  
ACTIVE 43 CAA   2
THICK_ACTIVE 60 CTA   24 Optional for TSMC; not available for Agilent/HP
POLY 46 CPG   3
SILICIDE_BLOCK 29 CSB   20 Optional for Agilent/HP; not available for AMI
N_PLUS_SELECT 45 CSN   4
P_PLUS_SELECT 44 CSP   4
CONTACT 25 CCC CCG 5, 6, 13  
POLY_CONTACT 47 CCP   5 Can be replaced by CONTACT
ACTIVE_CONTACT 48 CCA   6 Can be replaced by CONTACT
METAL1 49 CM1 CMF 7
VIA 50 CV1 CVA 8
METAL2 51 CM2 CMS 9
VIA2 61 CV2 CVS 14  
METAL3 62 CM3 CMT 15  
VIA3 30 CV3 CVT 21  
METAL4 31 CM4 CMQ 22  
CAP_TOP_METAL 35 CTM   28 Optional
VIA4 32 CV4 CVQ 25  
METAL5 33 CM5 CMP 26  
DEEP_N_WELL 38 CDNW   31  
GLASS 52 COG   10
PADS 26 XP  
Non-fab layer used to highlight pads
Comments -- CX     Comments



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