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Aragio Library
Instantiation for Universities
INTRODUCTION AND EXPLANATION
These instructions are for university account holders only. If your
organization is not affiliated with a university, please
contact Aragio
directly.
Aragio makes I/O libraries for the IBM 10LPe process available through
MOSIS to universities for use in designs fabricated through MOSIS.
These libraries are front-end kits only. They do not contain layout
information, SPICE, or netlists.
If you have not yet gained access to these libraries, please see
Aragio
Library Access for Universities.
Your place-and-route environment can, for example, provide a good
estimate of circuit timing using the front-end kit's abstractions.
They are not intended for SPICE-level design.
Using these front-end-only kits can create some limitations to the
design process. It is not possible to do full DRC, full
extraction/LVS, or full antenna checking. The entire process depends
on your place and route environment working in "correct by
construction" mode.
SUBMISSION
Submit your design at least one week prior to the
run closing deadline. In the
SPECIAL HANDLING parameter, request "Instantiation of Aragio IP."
Explicitly list the names and versions of the library or libraries
from which you want MOSIS to instantiate.
MOSIS will check whether you are using the most recent release
of that library, and if not, the design will be rejected.
Your GDS file may contain either calls to those cells without a
corresponding cell in the file, or a call to a dummy cell. If you use
a dummy cell, the dummy cell must contain no hierarchy in itself. We
replace those calls to point to real layout.
Be careful: this process is case-sensitive. Do not upshift/downshift
your cellnames during tapeout.
TAPE-OUT FORM
After you submit your project for fabrication, fill out the
Aragio Tapeout Form. Be sure to include the design number, and
the names and version numbers of the products used. Return the
completed form to by fax to the numbers at the top of the form.
INSTANTIATION
MOSIS will instantiate full layouts for you when you are ready to
fabricate your chip. We assume you will create a GDS file which
contains unresolved calls to Aragio cells and pads.
MOSIS will check whether you are using the most recent release of that
library, and if not, the design will be rejected.
If you are using the most recent release(s), MOSIS instantiates into
the incomplete submitted GDS, substitutes the layout, and informs the
design team of any issues.
The procedure is manual and labor intensive. Be certain you are
submitting final layout before requesting instantiation. Do not send
any Update Requests after the file has been instantiated, as this will
undo the instantiation.
This process has proved to be reliable. We instantiate about 15 to 20
designs a year, and we've never experienced a failure.
ADDITIONAL RESTRICTIONS
You are not permitted to see the resulting complete GDS. MOSIS will
not provide you with the GDS for your instantiated layout.
MOSIS cannot make any meaningful DRC results available, as the DRC
polygons reveal details of the Aragio cell layouts.
MOSIS never runs LVS on customer projects. LVS is a design issue: you
have a schematic, and you have a layout. MOSIS never handles any
schematics.
You cannot obtain cell layouts from MOSIS, nor will MOSIS refer you to
Aragio to obtain them.
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Related Links
MOSIS Policy For Document Access By University Accounts
Document Access for Universities
Account Liaison NDA (PDF)
Student, Staff and Non-Liaison Faculty NDA (PDF)
Mini-Proposal
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