In CMOS circuits the NMOS transistor is both an ESD (electrostatic
discharge) weak link and a device widely used in ESD protection
circuits (grounded- and gate-coupled NMOS transistors, low-voltage
triggered SCR devices, etc.).
By lowering the threshold current for thermal runaway after the device
enters the snapback region of operation, the shallow junctions and
lightly doped drains characteristic of deep sub-micron processes
contribute to the susceptibility of the NMOS device to damage from
ESD (Figure 1).
To produce more ESD-robust NMOS devices — specifically for use in
protection circuits — the ESD implant for TSMC CMOS processes, by
replacing the shallow, lightly doped junction of the standard device
with a deep, abrupt junction, lowers the local power density under
breakdown conditions by reducing both the current density and the
lateral NPN snapback voltage (Figure 2).
Normally the ESD implant will be used in conjunction with a thicker
gate oxide and a silicide block at the drain edge (to promote uniform
heating during an ESD event).
References:
[1] C. H. Diaz, T. E. Kopley, and P. A. Marcoux, "Building-In ESD/EOS
Reliability for Sub-Halfmicron CMOS Processes", IEEE
Trans. Electron Devices, vol. 43, no. 6, pp. 991--999, June
1996.
[2] A. Amerasekera, V. McNeil, M. Rodder, "Correlating Drain Junction
Scaling, Salicide Thickness, and Lateral NPN Behavior with the
ESD/EOS Performance of a 0.25 um CMOS Process", IEEE Electron
Device Meeting Technical Digest, pp. 893--896, 1996.
[3] A. Amerasekera, C. Duvvury, V. Reddy, M. Rodder, "Substrate
Triggering and Salicide Effects on ESD Performance and Protection
Circuit Design in Deep Submicron CMOS Processes", IEEE Electron
Device Society Meeting Technical Digest, pp. 547--550, 1995.
[4] A. Amerasekera, R. A. Chapman, "Technology Design for High Current
and ESD Robustness in a Deep Submicron CMOS Process", IEEE
Electron Device Letters, vol. 15, no. 10, pp. 383--385,
October
1994.
[5] C. Duvvury, "ESD: Design for IC Chip Quality and Reliability",
IEEE First International Symposium on Quality Electronic Design,
pp. 251--259, 2000.
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