There are many ways to define, calculate, estimate, and measure effective MOS channel dimensions, some biased more toward physical properties of the devices and some more toward goodness of fit of a particular model.

The formula above is valid for SPICE Level 3 and similar models, but is not applicable for BSIM3v3 because BSIM3v3 does not have an LD parameter, where LD represents the portion of the source-drain active area that lies under the gate,

The simple BSIM3v3 analog of LD is LINT, which we do extract and optimize.

The formula for effective channel length with MOSIS BSIM3v3 parameters is

L_effective = L_drawn - (2 * LINT)

(For this discussion we have simplified this expression somewhat. BSIM3v3 permits several more terms. Note that XL, which is not a BSIM3 parameter, but which is recognized by some modeling tools as a mask and process geometric bias factor (see FAQ on XL, XW), does not appear in the equation because it is incorporated into LINT during parameter extraction and optimization.)

Keep in mind that a process descriptor like "0.18 micron" is an approximation of the actual physical and-or effective electrical dimensions, the precise meaning of which varies considerably from vendor to vendor and from process to process and from NMOS to PMOS devices.

Also keep in mind that values for LINT, WINT, and other model parameters may be determined as much or more by the specific extraction and optimization procedures used to produce them as they are by the physical characteristics of the devices. A small change in a parameter optimization strategy can produce relatively large changes in LINT, for example, while still resulting in an overall set of model parameters that fits reasonably well.

In other words, you cannot properly interpret LINT, or the L_effective calculated from it, without considering the entire measurement process and extraction and optimization procedures that produced it.

Silicidization is the process of forming a surface layer of a refractory metal silicide on silicon. A metal, typically today titanium or cobalt, is deposited on the silicon (gate polysilicon and-or source drain regions), and a layer of silicide is formed when the two substances react at elevated temperatures.

Why do it? To lower the resistance of the polysilicon interconnect and-or the source-drain contact and sheet resistances.

In a "polycide" process only the polysilicon is silicided.

In a "silicide" process (usually implemented as a self-aligned silicidization - from whence the term "salicide") both gate polysilicon and source-drain regions are silicided.

Some processes provide a silicide blocking mask so that resistors can be constructed from the higher-resistance non-silicided material.