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The most frequently asked questions about design issues for projects
submitted to and fabricated by MOSIS.
MOSIS FAQs
Design Issues
1.0
What design formats will MOSIS accept?
2.0
What layout does MOSIS recommend for bonding pads?
3.0
Does using a guard ring affect pad spacing?
4.0
How do I draw a thick oxide transistor?
5.0
Do MOSIS design rules permit features drawn at a 45-degree
angle?
6.0
Questions about design conversion
-
6.1
How can I convert a design from AMI ABN_12 to AMI ABN_16?
-
6.2
How can I convert an SCMOS design from SCN4M_SUBM (TSMC 0.35
micron) to SCN5M_SUBM (TSMC 0.25 micron)?
7.0
What are the requirements for metal fill for CMP (chemical
mechanical polishing), and how do I incorporate these features into my
design?
-
7.1
What if my design doesn't meet the CMP requirements?
Will MOSIS fill it?
8.0
How do I avoid gate oxide damage from process-induced charging
(antenna effects)?
9.0
What precautions are necessary to protect MOSIS parts from
damage caused by electrostatic discharge (ESD)?
10.0
In the PDF file for the design rules, a suggested pad structure was
shown. This pad structure used all metal layers. It is possible to
make pads with only one or two metal layer? Or will this pose a
problem?
11.0
My die has large unpassivated areas. What precautions should I take?
12.0
Can my design be operated at a power supply voltage greater than the
voltage specified by the foundry as long as the voltage is less than
junction breakdown?
13.0
Can the current limits for metal interconnect in the design rules be
exceeded if the design is only a proof of concept prototype?
14.0
If I have several smaller circuits, can I put them together to
make up the 10 mm² minimum charge? Can I have sawstreets dividing
my
cells into sizes smaller than 10 mm² as long as the total area is 10
mm²?
15.0
Do I need to send MT, STI or FSRF forms with my TSMC layout?
16.0
In some cases, a layer when omitted is derived by MOSIS from other
drawn layers. Can I submit a partial layout for such a layer and have
MOSIS derive the rest from other layers I have drawn?
17.0
Can I include a digital image or logo in my layout?
1.0 What design formats will MOSIS accept?
-
MOSIS accepts designs in CIF or GDSII format.
For more information, see
MOSIS Layout Conventions for CIF and GDSII.
2.0 What layout does MOSIS recommend for bonding pads?
-
The minimum recommended pad layout for wire bonding is a 90 µm x
90 µm (3.5 mils x 3.5 mils) glass cut box over a 100 µm x
100
µm (3.9 mils x 3.9 mils) top metal box. For more information,
see
Bonding Pad Layout and Placement.
3.0 Does using a guard ring affect pad spacing?
-
Use of a guard ring does not effect pad spacing. Our general
recommendation is that pads are 100 µm x 100 µm with a
pitch of 170 µm (allows for pad edge to pad edge spacing of 70
µms). Smaller pads and tighter pitch are possible but not
without considering the exact location of the package cavity pins,
angle of wire to the pins and length of the wires.
4.0 How do I draw a thick oxide transistor?
-
For processes that provide a "thick oxide" option (for operation at
voltages above the standard process voltage), the MOSIS Thick_Active
layer selects which active areas receive the thick gate oxide. Active
by itself will have the standard process thin (gate) oxide. Active
overlapped by Thick_Active will have the thicker gate oxide.
Thick_Active by itself does nothing. Anything outside Active
(regardless of whether Thick_Active is present or not) gets field
oxide.
Poly crossing a thin oxide region (OD, or Active) surrounded by a
thick
oxide region (OD2, or Thick_Active) creates a thick oxide transistor.
5.0 Do MOSIS design rules permit features drawn at a 45-degree angle
(non-Manhattan features)?
-
It's best to avoid non-Manhattan layout. If a design requirement
demands a violation of this rule, make sure that non-orthogonal
features are very large, never approaching minimum width, spacing, or
overlap. Contacts and vias must be orthogonal. For additional
information, please see the MOSIS technical note,
"Mask Data Prep and
Manhattan Layout".
6.0 Questions about design conversion.
6.1 How can I convert a design from AMI ABN_12 to AMI ABN_16?
-
Both ABN_12 and ABN_16 are in MOSIS "standard" SCMOS rule sets.
Lambda must be redefined from 0.6 (for AMI ABN_12) to 0.8 (for AMI
ABN_16). Note that for ABN_16, MOSIS recommends that
Rule 2.1
be increased from 3 lambda (for AMI ABN_12) to 5 lambda (for AMI
ABN_16). Pads designed specifically for ABN_16 should be used, since
in general, pads cannot simply be scaled. Links to ABN_16 pads are
available from the
SCMOS Design
Kits page.
ABN_16 permits smaller lambda values for metal-1 spacing:
Rule 7.2
(3 lambda in ABN_12, 2 lambda in ABN_16), and metal-2 spacing:
Rule
9.2
(4 lambda in ABN_12, 3 lambda in ABN_16), plus the corresponding
wide-metal rules 7.4 and 9.4.
6.2 How can I convert an SCMOS design from SCN4M_SUBM (TSMC 0.35
micron) to SCN5M_SUBM (TSMC 0.25 micron)?
-
For single-poly TSMC 0.35 micron designs, lambda must be redefined
from 0.2 (for TSMC 0.35) to 0.15 (for TSMC 0.25). Pads should not be
directly scaled, so the pad ring may need special attention.
This includes adding via4 and metal5 to the TSMC 0.25 pad stacks.
Note
that TSMC 0.25 might permit smaller lambda values for
Rule
22
(metal4) than the original TSMC 0.35 design. TSMC 0.35 Poly2-Poly1
capacitors should be converted to TSMC_025 M4_Prime-M4 capacitors.
7.0 What are the requirements for metal fill for CMP
(chemical mechanical polishing), and how do I incorporate these
features into my design?
-
See
MOSIS CMP and Antenna Rules.
-
7.1 What if my design doesn't meet the CMP
requirements? Will MOSIS fill it?
-
If a design contains layers which do not meet density requirements for
chemical mechanical polishing (CMP), then other designs on the reticle
must make up for the deficit, or there must be enough blank area
between designs to permit MOSIS to add sufficient fill.
If layer density requirements cannot be met by these means, then MOSIS
may exclude layout that does not meet the requirements. Please note
that MOSIS cannot waive the metal filling rules.
When CMP-related density requirements were first imposed by our
fabrication vendors, many design environments did not support easy
insertion of "fill" structures. To facilitate the transition to
processes constrained by CMP, MOSIS started adding this fill to
customer designs whenever a design failed to meet the density
requirements. Although adding fill is relatively straightforward for
simpler digital designs, the placement of fill elements can affect the
operation of RF and other analog circuits, and also high-speed digital
circuits with critical timing paths. For this reason, MOSIS now
strongly encourages designers to provide the required CMP fill in
their layout.
Customers can specifically request that MOSIS fill their layout by
using the "fill authorized" parameter available in the NEW-PROJECT and
FABRICATE requests. Because of potential effects on circuit
performance, MOSIS does not recommend this.
Two ways you can meet the CMP requirement are to fill your layout or
to add a filled "doughnut" around your design. In the latter case,
the surrounding area will be part of your layout, and will be included
in pricing calculations.
8.0 How do I avoid gate oxide damage from process-induced charging
(antenna effects)?
-
See the
Antenna Rules
9.0 What precautions are necessary to protect MOSIS parts from
damage caused by electrostatic discharge (ESD)?
-
MOSIS handles wafers and singulated and packaged parts in a
static-controlled environment with regulated humidity and conductive
or dissipative flooring, work surfaces, carriers, and tools.
Personnel wear conductive outer garments and gloves and a conductive
wrist strap when handling any semiconductor product material. Parts
are shipped in static-dissipative, protective packaging.
Designers and end users must enforce appropriate protective measures
against static discharge damage. ESD pads should be employed whenever
possible, and parts should be handled only by trained operators in a
static-controlled environment.
10.0
In the PDF file for the design rules, a suggested pad structure was
shown. This pad structure used all metal layers. It is possible to
make pads with only one or two metal layer? Or will this pose a
problem?
-
Pads (with each metal layer) are recommended but not required. Damage
may occur to the top metal layer during wire bonding due to the lack
of support from metal layers below. MOSIS is not responsible for any
bonding issues resulting pads where the recommended design rules are
not used.
11.0
My die has large unpassivated areas. What precautions should I take?
-
To alert MOSIS to the presence of your unpassivated design, please
send an Update request (web form
or e-mail
template) with a SPECIAL-HANDLING parameter with the following
text, plus any additional comments you wish to provide:
-
"UNPASSIVATED DIE. Nothing may contact the wafer top surface. Wafer
carriers and shipping containers must contact wafers only at the
edges. Use tweezers to handle individual dice only from the sides and
bottom. Place all loose dice, including spares, in GEL-PAK's for
shipping and storage."
This UNPASSIVATED DIE special handling is intended for open areas on
the die surface where damage can occur if contacted. If glass
openings have MEMS structures that will be etched in post processing,
or the glass openings are over bonding or probe pads, this
unpassivated
special handling should not be required.
NOTE: Although we and our vendors take special care with wafers known
to contain unpassivated active circuit areas, MOSIS cannot guarantee
the electrical or mechanical integrity of unpassivated designs.
12.0
Can my design be operated at a power supply voltage greater than the
voltage specified by the foundry as long as the voltage is less than
junction breakdown?
-
Failure to operate a design within the voltage limits specified by the
foundry will result in significant risk of early failure caused by
either Time Dependent Dielectric Breakdown (TDDB) or Hot Carrier
Damage
(HCD). HCD will have the most rapid measurable effect, which leads to
a shift in transistor electrical characteristics that may cause
circuits to fail. TDDB is the catastrophic failure of gate oxide that
will lead to a non-functional transistor. It is advisable not to
exceed recommended power supply voltage limits and any attempt to use
higher than recommended voltage will be at the designer's risk.
Further discussion on CMOS failure mechanisms can be found in a short
tutorial on Reliability in CMOS IC
Design.
13.0
Can the current limits for metal interconnect in the design rules be
exceeded if the design is only a proof of concept prototype?
-
Current density limits, specified in the design rules, are defined by
foundries to provide reasonable assurance that metal interconnects
will not fail because of electromigration within about twenty years.
Modest current density overstress will certainly shorten interconnect
lifetimes, but the lifetime versus current density tradeoffs involve
knowledge about electromigration model parameters that are considered
proprietary by foundries. Designers must conform to design rules in
order to have reasonable assurance of a reliable design. More
information about electromigration will be found in a short tutorial
on Reliability in CMOS IC Design.
14.0
If I have several smaller circuits, can I put them together to
make up the 10 mm² minimum charge? Can I have sawstreets dividing
my
cells into sizes smaller than 10 mm² as long as the total area is 10
mm²?
-
Yielding to incremental cost issues and concerns over reduced yield
due to increased handling, MOSIS does not offer a sub-dice service but
we accomplish the same thing by having customers submit their designs
individually. The charge for submitting 2 or more designs with a
total area of 10 mm² is slightly higher than submitting one 10
mm² layout. For pricing, please send a
Request for Custom Quote
and provide the exact sizes of each individual layout.
15.0
Do I need to send MT, STI or FSRF forms with my TSMC layout?
-
MOSIS generates and submits the foundry MT, STI, and FSRF forms for
wafer lots fabricated at TSMC, based on the requirements for all
designs included on a given run. Designers should not submit these
forms.
MOSIS customers must adhere to the
posted layer map.
No other layer mapping may be specified.
Please note that not all TSMC options specified on MT, FSRF and STI
forms are available on MOSIS multi-project wafers runs -- examples
include the number of metal layers and the location of CTM. See the
following for more details.
-
http://www.mosis.com/products/fab/vendors/
Options not available as the MOSIS default may be ordered from MOSIS
for an incremental fee. Since the non-default options usually require
ordering an additional lot of wafers, the incremental fee often runs
$30,000 or more depending on the technology.
16.0
In some cases, a layer when omitted is derived by MOSIS from other
drawn layers. Can I submit a partial layout for such a layer and have
MOSIS derive the rest from other layers I have drawn?
-
MOSIS does not create a layer partially from a layer drawn by the
customer and partially derived from other layers.
17.0
Can I include a digital image or logo in my layout?
-
MOSIS discourages designers from including logos or other non-circuit
features in layout submitted for fabrication. In nearly every case,
these artifacts violate design rules and create unnecessary error
flags during the creation and inspection of the masks. These errors
must be reviewed and evaluated by MOSIS staff. The entire run is
delayed while this review takes place.
For further details, please see
Sub-minimum Features Not
Allowed.
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